8( Rcompulab,omap3-sbc-t3530compulab,omap3-cm-t3530ti,omap3430ti,omap34xxti,omap3 +!7CompuLab SBC-T3530 with CM-T3530chosenaliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/serial@4806a000T/ocp@68000000/serial@4806c000\/ocp@68000000/serial@49020000d/dvi-connectorm/svideo-connectorcpus+cpu@0arm,cortex-a8vcpucpupmu@54000000arm,cortex-a8-pmuTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2ivadsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-bush +l3_mainl4@48000000ti,omap3-l4-coresimple-bus+ Hscm@2000ti,omap3-scmsimple-bus + pinmux@30 ti,omap3-padconfpinctrl-single08+6Sdefaultapinmux_uart3_pinsknppinmux_mmc1_pins0kpinmux_green_led_pinskpinmux_dss_dpi_pins_commonkpinmux_dss_dpi_pins_cm_t35x0kpinmux_ads7846_pinskpinmux_mcspi1_pins kpinmux_i2c1_pinskpinmux_mcbsp2_pins k pinmux_smsc1_pinskjpinmux_hsusb0_pins`krtvxz|~ pinmux_twl4030_pinskApinmux_mmc2_pinsPk(*,.02468:pinmux_smsc2_pinsk pinmux_tfp410_pinskpinmux_i2c3_pinskpinmux_sb_t35_audio_ampk#pinmux_sb_t35_usb_hub_pinskscm_conf@270sysconsimple-busp0+ p0pbias_regulator@2b0ti,pbias-omap3ti,pbias-omappbias_mmc_omap2430pbias_mmc_omap2430w@-clocks+mcbsp5_mux_fck@68ti,composite-mux-clockh mcbsp5_fckti,composite-clock mcbsp1_mux_fck@4ti,composite-mux-clock mcbsp1_fckti,composite-clock mcbsp2_mux_fck@4ti,composite-mux-clock mcbsp2_fckti,composite-clockmcbsp3_mux_fck@68ti,composite-mux-clock hmcbsp3_fckti,composite-clockmcbsp4_mux_fck@68ti,composite-mux-clock hmcbsp4_fckti,composite-clockclockdomainspinmux@a00 ti,omap3-padconfpinctrl-single \+6pinmux_twl4030_vpins ktarget-module@480a6000ti,sysc-omap2ti,syscH `DH `HH `Lrevsyscsyss  ick+ H ` aes1@0 ti,omap3-aesP  txrxtarget-module@480c5000ti,sysc-omap2ti,syscH PDH PHH PLrevsyscsyss  ick+ H P aes2@0 ti,omap3-aesPABtxrxprm@48306000 ti,omap3-prmH0`@ clocks+virt_16_8m_ck fixed-clock(Yosc_sys_ck@d40 ti,mux-clock @sys_ck@1270ti,divider-clock8pC"sys_clkout1@d70ti,gate-clock pdpll3_x2_ckfixed-factor-clockZedpll3_m2x2_ckfixed-factor-clockZe!dpll4_x2_ckfixed-factor-clock Zecorex2_fckfixed-factor-clock!Ze#wkup_l4_ickfixed-factor-clock"ZeRcorex2_d3_fckfixed-factor-clock#Zecorex2_d5_fckfixed-factor-clock#Zeclockdomainscm@48004000 ti,omap3-cmH@@clocks+dummy_apb_pclk fixed-clock(omap_32k_fck fixed-clock(Dvirt_12m_ck fixed-clock(virt_13m_ck fixed-clock(]@virt_19200000_ck fixed-clock($virt_26000000_ck fixed-clock(virt_38_4m_ck fixed-clock(Idpll4_ck@d00ti,omap3-dpll-per-clock"" D 0 dpll4_m2_ck@d48ti,divider-clock 8? HC$dpll4_m2x2_mul_ckfixed-factor-clock$Ze%dpll4_m2x2_ck@d00ti,gate-clock% o&omap_96m_alwon_fckfixed-factor-clock&Ze-dpll3_ck@d00ti,omap3-dpll-core-clock"" @ 0dpll3_m3_ck@1140ti,divider-clock8@C'dpll3_m3x2_mul_ckfixed-factor-clock'Ze(dpll3_m3x2_ck@d00ti,gate-clock(  o)emu_core_alwon_ckfixed-factor-clock)Zefsys_altclk fixed-clock(2mcbsp_clks fixed-clock(dpll3_m2_ck@d40ti,divider-clock8 @Ccore_ckfixed-factor-clockZe*dpll1_fck@940ti,divider-clock*8 @C+dpll1_ck@904ti,omap3-dpll-clock"+  $ @ 4dpll1_x2_ckfixed-factor-clockZe,dpll1_x2m2_ck@944ti,divider-clock,8 DC@cm_96m_fckfixed-factor-clock-Ze.omap_96m_fck@d40 ti,mux-clock." @Idpll4_m3_ck@e40ti,divider-clock 8 @C/dpll4_m3x2_mul_ckfixed-factor-clock/Ze0dpll4_m3x2_ck@d00ti,gate-clock0 o1omap_54m_fck@d40 ti,mux-clock12 @<cm_96m_d2_fckfixed-factor-clock.Ze3omap_48m_fck@d40 ti,mux-clock32 @4omap_12m_fckfixed-factor-clock4ZeKdpll4_m4_ck@e40ti,divider-clock 8@C5dpll4_m4x2_mul_ckti,fixed-factor-clock56dpll4_m4x2_ck@d00ti,gate-clock6 odpll4_m5_ck@f40ti,divider-clock 8?@C7dpll4_m5x2_mul_ckti,fixed-factor-clock78dpll4_m5x2_ck@d00ti,gate-clock8 ondpll4_m6_ck@1140ti,divider-clock 8?@C9dpll4_m6x2_mul_ckfixed-factor-clock9Ze:dpll4_m6x2_ck@d00ti,gate-clock: o;emu_per_alwon_ckfixed-factor-clock;Zegclkout2_src_gate_ck@d70 ti,composite-no-wait-gate-clock* p=clkout2_src_mux_ck@d70ti,composite-mux-clock*".< p>clkout2_src_ckti,composite-clock=>?sys_clkout2@d70ti,divider-clock?8@ pmpu_ckfixed-factor-clock@ZeAarm_fck@924ti,divider-clockA $8emu_mpu_alwon_ckfixed-factor-clockAZehl3_ick@a40ti,divider-clock*8 @CBl4_ick@a40ti,divider-clockB8 @CCrm_ick@c40ti,divider-clockC8 @Cgpt10_gate_fck@a00ti,composite-gate-clock"  Egpt10_mux_fck@a40ti,composite-mux-clockD" @Fgpt10_fckti,composite-clockEFgpt11_gate_fck@a00ti,composite-gate-clock"  Ggpt11_mux_fck@a40ti,composite-mux-clockD" @Hgpt11_fckti,composite-clockGHcore_96m_fckfixed-factor-clockIZemmchs2_fck@a00ti,wait-gate-clock mmchs1_fck@a00ti,wait-gate-clock i2c3_fck@a00ti,wait-gate-clock i2c2_fck@a00ti,wait-gate-clock i2c1_fck@a00ti,wait-gate-clock mcbsp5_gate_fck@a00ti,composite-gate-clock   mcbsp1_gate_fck@a00ti,composite-gate-clock   core_48m_fckfixed-factor-clock4ZeJmcspi4_fck@a00ti,wait-gate-clockJ mcspi3_fck@a00ti,wait-gate-clockJ mcspi2_fck@a00ti,wait-gate-clockJ mcspi1_fck@a00ti,wait-gate-clockJ uart2_fck@a00ti,wait-gate-clockJ uart1_fck@a00ti,wait-gate-clockJ  core_12m_fckfixed-factor-clockKZeLhdq_fck@a00ti,wait-gate-clockL core_l3_ickfixed-factor-clockBZeMsdrc_ick@a10ti,wait-gate-clockM gpmc_fckfixed-factor-clockMZecore_l4_ickfixed-factor-clockCZeNmmchs2_ick@a10ti,omap3-interface-clockN mmchs1_ick@a10ti,omap3-interface-clockN hdq_ick@a10ti,omap3-interface-clockN mcspi4_ick@a10ti,omap3-interface-clockN mcspi3_ick@a10ti,omap3-interface-clockN mcspi2_ick@a10ti,omap3-interface-clockN mcspi1_ick@a10ti,omap3-interface-clockN i2c3_ick@a10ti,omap3-interface-clockN i2c2_ick@a10ti,omap3-interface-clockN i2c1_ick@a10ti,omap3-interface-clockN uart2_ick@a10ti,omap3-interface-clockN uart1_ick@a10ti,omap3-interface-clockN  gpt11_ick@a10ti,omap3-interface-clockN  gpt10_ick@a10ti,omap3-interface-clockN  mcbsp5_ick@a10ti,omap3-interface-clockN  mcbsp1_ick@a10ti,omap3-interface-clockN  omapctrl_ick@a10ti,omap3-interface-clockN dss_tv_fck@e00ti,gate-clock<dss_96m_fck@e00ti,gate-clockIdss2_alwon_fck@e00ti,gate-clock"dummy_ck fixed-clock(gpt1_gate_fck@c00ti,composite-gate-clock" Ogpt1_mux_fck@c40ti,composite-mux-clockD" @Pgpt1_fckti,composite-clockOPaes2_ick@a10ti,omap3-interface-clockN wkup_32k_fckfixed-factor-clockDZeQgpio1_dbck@c00ti,gate-clockQ sha12_ick@a10ti,omap3-interface-clockN wdt2_fck@c00ti,wait-gate-clockQ wdt2_ick@c10ti,omap3-interface-clockR wdt1_ick@c10ti,omap3-interface-clockR gpio1_ick@c10ti,omap3-interface-clockR omap_32ksync_ick@c10ti,omap3-interface-clockR gpt12_ick@c10ti,omap3-interface-clockR gpt1_ick@c10ti,omap3-interface-clockR per_96m_fckfixed-factor-clock-Ze per_48m_fckfixed-factor-clock4ZeSuart3_fck@1000ti,wait-gate-clockS gpt2_gate_fck@1000ti,composite-gate-clock"Tgpt2_mux_fck@1040ti,composite-mux-clockD"@Ugpt2_fckti,composite-clockTUgpt3_gate_fck@1000ti,composite-gate-clock"Vgpt3_mux_fck@1040ti,composite-mux-clockD"@Wgpt3_fckti,composite-clockVWgpt4_gate_fck@1000ti,composite-gate-clock"Xgpt4_mux_fck@1040ti,composite-mux-clockD"@Ygpt4_fckti,composite-clockXYgpt5_gate_fck@1000ti,composite-gate-clock"Zgpt5_mux_fck@1040ti,composite-mux-clockD"@[gpt5_fckti,composite-clockZ[gpt6_gate_fck@1000ti,composite-gate-clock"\gpt6_mux_fck@1040ti,composite-mux-clockD"@]gpt6_fckti,composite-clock\]gpt7_gate_fck@1000ti,composite-gate-clock"^gpt7_mux_fck@1040ti,composite-mux-clockD"@_gpt7_fckti,composite-clock^_gpt8_gate_fck@1000ti,composite-gate-clock" `gpt8_mux_fck@1040ti,composite-mux-clockD"@agpt8_fckti,composite-clock`agpt9_gate_fck@1000ti,composite-gate-clock" bgpt9_mux_fck@1040ti,composite-mux-clockD"@cgpt9_fckti,composite-clockbcper_32k_alwon_fckfixed-factor-clockDZedgpio6_dbck@1000ti,gate-clockdgpio5_dbck@1000ti,gate-clockdgpio4_dbck@1000ti,gate-clockdgpio3_dbck@1000ti,gate-clockdgpio2_dbck@1000ti,gate-clockd wdt3_fck@1000ti,wait-gate-clockd per_l4_ickfixed-factor-clockCZeegpio6_ick@1010ti,omap3-interface-clockegpio5_ick@1010ti,omap3-interface-clockegpio4_ick@1010ti,omap3-interface-clockegpio3_ick@1010ti,omap3-interface-clockegpio2_ick@1010ti,omap3-interface-clocke wdt3_ick@1010ti,omap3-interface-clocke uart3_ick@1010ti,omap3-interface-clocke uart4_ick@1010ti,omap3-interface-clockegpt9_ick@1010ti,omap3-interface-clocke gpt8_ick@1010ti,omap3-interface-clocke gpt7_ick@1010ti,omap3-interface-clockegpt6_ick@1010ti,omap3-interface-clockegpt5_ick@1010ti,omap3-interface-clockegpt4_ick@1010ti,omap3-interface-clockegpt3_ick@1010ti,omap3-interface-clockegpt2_ick@1010ti,omap3-interface-clockemcbsp2_ick@1010ti,omap3-interface-clockemcbsp3_ick@1010ti,omap3-interface-clockemcbsp4_ick@1010ti,omap3-interface-clockemcbsp2_gate_fck@1000ti,composite-gate-clockmcbsp3_gate_fck@1000ti,composite-gate-clockmcbsp4_gate_fck@1000ti,composite-gate-clockemu_src_mux_ck@1140 ti,mux-clock"fgh@iemu_src_ckti,clkdm-gate-clockijpclk_fck@1140ti,divider-clockj8@Cpclkx2_fck@1140ti,divider-clockj8@Catclk_fck@1140ti,divider-clockj8@Ctraceclk_src_fck@1140 ti,mux-clock"fgh@ktraceclk_fck@1140ti,divider-clockk 8@Csecure_32k_fck fixed-clock(lgpt12_fckfixed-factor-clocklZewdt1_fckfixed-factor-clocklZesecurity_l4_ick2fixed-factor-clockCZemaes1_ick@a14ti,omap3-interface-clockm rng_ick@a14ti,omap3-interface-clockm sha11_ick@a14ti,omap3-interface-clockm des1_ick@a14ti,omap3-interface-clockm cam_mclk@f00ti,gate-clockncam_ick@f10!ti,omap3-no-wait-interface-clockCcsi2_96m_fck@f00ti,gate-clocksecurity_l3_ickfixed-factor-clockBZeopka_ick@a14ti,omap3-interface-clocko icr_ick@a10ti,omap3-interface-clockN des2_ick@a10ti,omap3-interface-clockN mspro_ick@a10ti,omap3-interface-clockN mailboxes_ick@a10ti,omap3-interface-clockN ssi_l4_ickfixed-factor-clockCZevsr1_fck@c00ti,wait-gate-clock" sr2_fck@c00ti,wait-gate-clock" sr_l4_ickfixed-factor-clockCZedpll2_fck@40ti,divider-clock*8@Cpdpll2_ck@4ti,omap3-dpll-clock"p$@4qdpll2_m2_ck@44ti,divider-clockq8DCriva2_ck@0ti,wait-gate-clockrmodem_fck@a00ti,omap3-interface-clock" sad2d_ick@a10ti,omap3-interface-clockB mad2d_ick@a18ti,omap3-interface-clockB mspro_fck@a00ti,wait-gate-clock ssi_ssr_gate_fck_3430es2@a00 ti,composite-no-wait-gate-clock# sssi_ssr_div_fck_3430es2@a40ti,composite-divider-clock# @$tssi_ssr_fck_3430es2ti,composite-clockstussi_sst_fck_3430es2fixed-factor-clockuZehsotgusb_ick_3430es2@a10"ti,omap3-hsotgusb-interface-clockM ssi_ick_3430es2@a10ti,omap3-ssi-interface-clockv usim_gate_fck@c00ti,composite-gate-clockI  sys_d2_ckfixed-factor-clock"Zexomap_96m_d2_fckfixed-factor-clockIZeyomap_96m_d4_fckfixed-factor-clockIZezomap_96m_d8_fckfixed-factor-clockIZe{omap_96m_d10_fckfixed-factor-clockIZe |dpll5_m2_d4_ckfixed-factor-clockwZe}dpll5_m2_d8_ckfixed-factor-clockwZe~dpll5_m2_d16_ckfixed-factor-clockwZedpll5_m2_d20_ckfixed-factor-clockwZeusim_mux_fck@c40ti,composite-mux-clock("xyz{|}~ @Cusim_fckti,composite-clockusim_ick@c10ti,omap3-interface-clockR  dpll5_ck@d04ti,omap3-dpll-clock""  $ L 4dpll5_m2_ck@d50ti,divider-clock8 PCwsgx_gate_fck@b00ti,composite-gate-clock* core_d3_ckfixed-factor-clock*Zecore_d4_ckfixed-factor-clock*Zecore_d6_ckfixed-factor-clock*Zeomap_192m_alwon_fckfixed-factor-clock&Zecore_d2_ckfixed-factor-clock*Zesgx_mux_fck@b40ti,composite-mux-clock . @sgx_fckti,composite-clocksgx_ick@b10ti,wait-gate-clockB cpefuse_fck@a08ti,gate-clock" ts_fck@a08ti,gate-clockD usbtll_fck@a08ti,wait-gate-clockw usbtll_ick@a18ti,omap3-interface-clockN mmchs3_ick@a10ti,omap3-interface-clockN mmchs3_fck@a00ti,wait-gate-clock dss1_alwon_fck_3430es2@e00ti,dss-gate-clockdss_ick_3430es2@e10ti,omap3-dss-interface-clockCusbhost_120m_fck@1400ti,gate-clockwusbhost_48m_fck@1400ti,dss-gate-clock4usbhost_ick@1410ti,omap3-dss-interface-clockCclockdomainscore_l3_clkdmti,clockdomaindpll3_clkdmti,clockdomaindpll1_clkdmti,clockdomainper_clkdmti,clockdomainhemu_clkdmti,clockdomainjdpll4_clkdmti,clockdomain wkup_clkdmti,clockdomain$dss_clkdmti,clockdomaincore_l4_clkdmti,clockdomaincam_clkdmti,clockdomainiva2_clkdmti,clockdomaindpll2_clkdmti,clockdomainqd2d_clkdmti,clockdomain dpll5_clkdmti,clockdomainsgx_clkdmti,clockdomainusbhost_clkdmti,clockdomain target-module@48320000ti,sysc-omap2ti,syscH2H2 revsyscQfckick+ H2counter@0ti,omap-counter32k interrupt-controller@48200000ti,omap3-intcH target-module@48056000ti,sysc-omap2ti,syscH`H`,H`(revsyscsyss#   Mick+ H`dma-controller@0ti,omap3430-sdmati,omap-sdma  )`gpio@48310000ti,omap3-gpioH1gpio16HXgpio@49050000ti,omap3-gpioIgpio2HXgpio@49052000ti,omap3-gpioI gpio3HX gpio@49054000ti,omap3-gpioI@ gpio4HXgpio@49056000ti,omap3-gpioI`!gpio5HXgpio@49058000ti,omap3-gpioI"gpio6HX serial@4806a000ti,omap3-uartH dH12txrxuart1(lserial@4806c000ti,omap3-uartHdI34txrxuart2(lserial@49020000ti,omap3-uartIdJ56txrxuart3(lSdefaultai2c@48070000 ti,omap3-i2cH8txrx+i2c1Sdefaulta(at24@50 atmel,24c02xPtwl@48H  ti,twl4030Sdefaultaaudioti,twl4030-audiocodecrtcti,twl4030-rtc bciti,twl4030-bci  vacwatchdogti,twl4030-wdtregulator-vaux1ti,twl4030-vaux1regulator-vaux2ti,twl4030-vaux2regulator-vaux3ti,twl4030-vaux3regulator-vaux4ti,twl4030-vaux4regulator-vdd1ti,twl4030-vdd1 ' regulator-vdacti,twl4030-vdacw@w@regulator-vioti,twl4030-vioregulator-vintana1ti,twl4030-vintana1regulator-vintana2ti,twl4030-vintana2regulator-vintdigti,twl4030-vintdigregulator-vmmc1ti,twl4030-vmmc1:0regulator-vmmc2ti,twl4030-vmmc2:0regulator-vusb1v5ti,twl4030-vusb1v5regulator-vusb1v8ti,twl4030-vusb1v8regulator-vusb3v1ti,twl4030-vusb3v1regulator-vpll1ti,twl4030-vpll1regulator-vpll2ti,twl4030-vpll2w@w@regulator-vsimti,twl4030-vsimw@-gpioti,twl4030-gpioHXtwl4030-usbti,twl4030-usb  pwmti,twl4030-pwmpwmledti,twl4030-pwmledpwrbuttonti,twl4030-pwrbuttonkeypadti,twl4030-keypad $/0iglj. madcti,twl4030-madc<i2c@48072000 ti,omap3-i2cH 9txrx+i2c2i2c@48060000 ti,omap3-i2cH=txrx+i2c3(Sdefaultaat24@50 atmel,24c02xPmailbox@48094000ti,omap3-mailboxmailboxH @NZldsp ~ spi@48098000ti,omap2-mcspiH A+mcspi1@#$%&'()* tx0rx0tx1rx1tx2rx2tx3rx3Sdefaultaads7846@0Sdefaulta ti,ads7846`   0@spi@4809a000ti,omap2-mcspiH B+mcspi2 +,-.tx0rx0tx1rx1spi@480b8000ti,omap2-mcspiH [+mcspi3 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compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2serial0serial1serial2display0display1device_typeregclocksclock-namesclock-latencyoperating-points-v2cpu0-supplyinterruptsti,hwmodsranges#pinctrl-cells#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-namespinctrl-0pinctrl-single,pinsphandlesysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsti,bit-shiftreg-namesti,sysc-maskti,sysc-sidleti,syss-maskdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividersti,sysc-midle#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedpagesizebci3v1-supplyio-channelsio-channel-namesti,use-ledsti,pullupsusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columnslinux,keymap#io-channel-cells#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csvcc-supplyspi-max-frequencypendown-gpioti,x-minti,x-maxti,y-minti,y-maxti,x-plate-ohmsti,pressure-maxti,debounce-maxti,debounce-tolti,debounce-repwakeup-sourceti,dual-voltpbias-supplybus-widthvmmc-supplycd-gpiosnon-removablecap-power-off-cardstatus#iommu-cellsti,#tlb-entriesinterrupt-namesti,buffer-size#sound-dai-cellsti,no-reset-on-initti,no-idleti,timer-alwonassigned-clocksassigned-clock-parentsti,timer-dspti,timer-pwmti,timer-secureport1-modeport2-moderemote-wakeup-connectedphysgpmc,num-csgpmc,num-waitpinsnand-bus-widthgpmc,device-widthti,nand-ecc-optgpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,we-on-nsgpmc,we-off-nsgpmc,oe-on-nsgpmc,oe-off-nsgpmc,page-burst-access-nsgpmc,access-nsgpmc,cycle2cycle-delay-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,wr-access-nsgpmc,wr-data-mux-bus-nslabelbank-widthgpmc,cycle2cycle-samecsengpmc,cycle2cycle-diffcsengpmc,bus-turnaround-nsgpmc,wait-monitoring-nsgpmc,clk-activation-nsvddvario-supplyvdd33a-supplyreg-io-widthsmsc,save-mac-addressmultipointnum-epsram-bitsinterface-typeusb-phyphy-namespowervdda-supplyremote-endpointti,channelsdata-linesiommusti,phy-type#thermal-sensor-cellsopp-hzopp-microvoltopp-supported-hwopp-suspendturbo-modepolling-delay-passivepolling-delaycoefficientsthermal-sensorslinux,default-triggerstartup-delay-usreset-gpiosti,modelti,mcbspregulator-always-onenable-active-highpowerdown-gpios