I%HDd(D EBV SOCrates0!ebv,socratesaltr,socfpga-cyclone5altr,socfpgaaliases,/soc/serial0@ffc020004/soc/serial1@ffc03000Pnand@ff900000!altr,socfpga-denali-nand|anand_datadenali_reg  ,-#nandnand_xecc/$ ?disabledsram@ffff0000 !mmio-sram|*spi@ff705000!cdns,qspi-nor|pP k{./%?okayflash@0 !n25q256a|22?okayrstmgr@ffd05000  !altr,rst-mgr|Psnoop-control-unit@fffec000!arm,cortex-a9-scu|sdr@ffc25000!altr,sdr-ctlsyscon|P/=/sdramedac!altr,sdram-edac)/ 'spi@fff00000!snps,dw-apb-ssi| 90/2 ?disabledspi@fff01000!snps,dw-apb-ssi| 90/3 ?disabledsysmgr@ffd08000!altr,sys-mgrsyscon|Ѐ@@Ѐ%timer@fffec600!arm,cortex-a9-twd-timer|  1timer0@ffc08000!snps,dw-apb-timer |)#timer/*timertimer1@ffc09000!snps,dw-apb-timer |)#timer/+timertimer2@ffd00000!snps,dw-apb-timer | #timer/(timertimer3@ffd01000!snps,dw-apb-timer | #timer/)timerserial0@ffc02000!snps,dw-apb-uart|  PZ)g22ltxrx/0serial1@ffc03000!snps,dw-apb-uart|0 PZ)g22ltxrx/1usbphyv!usb-nop-xceiv?okay4usb@ffb00000 !snps,dwc2| }3#otg/"dwc24 usb2-phy ?disabledusb@ffb40000 !snps,dwc2| 3#otg/#dwc24 usb2-phy ?disabledwatchdog@ffd02000 !snps,dw-wdt|   /&?okaywatchdog@ffd03000 !snps,dw-wdt|0  /' ?disabledchosen earlyprintkserial0:115200n8memory@0pmemory|@gpio-leds !gpio-ledsled0led:green:heartbeat G5 heartbeatled1 led:green:D7 G6led2 led:green:D8 G6 #address-cells#size-cellsmodelcompatibleserial0serial1timer0timer1timer2timer3ethernet0enable-methoddevice_typeregnext-level-cachephandleinterrupt-parentinterruptsinterrupt-affinity#interrupt-cellsinterrupt-controllerranges#dma-cells#dma-channels#dma-requestsclocksclock-namesresetsfpga-mgrstatus#clock-cellsclock-frequencydiv-regfixed-dividerclk-gateclk-phasealtr,sysmgr-sysconinterrupt-namesmac-addressreset-namessnps,multicast-filter-binssnps,perfect-filter-entriestx-fifo-depthrx-fifo-depthphy-modegpio-controller#gpio-cellssnps,nr-gpiosiramcache-unifiedcache-levelarm,tag-latencyarm,data-latencyprefetch-dataprefetch-instrarm,shared-overridearm,double-linefillarm,double-linefill-incrarm,double-linefill-wraparm,prefetch-droparm,prefetch-offsetbroken-cdbus-widthcap-mmc-highspeedcap-sd-highspeedreg-namescdns,fifo-depthcdns,fifo-widthcdns,trigger-addressspi-max-frequencym25p,fast-readcdns,read-delaycdns,tshsl-nscdns,tsd2d-nscdns,tchsh-nscdns,tslch-ns#reset-cellsaltr,modrst-offsetaltr,sdr-sysconnum-cscpu1-start-addrreg-shiftreg-io-widthdmasdma-names#phy-cellsphysphy-namesbootargsstdout-pathlabellinux,default-trigger