� ��z8s(�r�&firefly,roc-rk3328-ccrockchip,rk3328 +7Firefly roc-rk3328-ccaliases=/serial@ff110000E/serial@ff120000M/serial@ff130000U/i2c@ff150000Z/i2c@ff160000_/i2c@ff170000d/i2c@ff180000i/ethernet@ff540000s/ethernet@ff550000cpus+cpu@0}cpuarm,cortex-a53arm,armv8����x�psci����cpu@1}cpuarm,cortex-a53arm,armv8����x�psci���cpu@2}cpuarm,cortex-a53arm,armv8����x�psci���cpu@3}cpuarm,cortex-a53arm,armv8����x�psci��� l2-cache0cache�opp_table0operating-points-v2�opp-408000000Q�~�#�@4opp-600000000#�F~�#�@opp-8160000000�,B@#�@opp-1008000000<���#�@opp-1200000000G���(#�@opp-1296000000M?d� #�@amba simple-bus+@dmac@ff1f0000arm,pl330arm,primecell��@G�� Rapb_pclk^� arm-pmuarm,cortex-a53-pmu0Gdefgi psciarm,psci-1.0arm,psci-0.2�smctimerarm,armv8-timer0G   xin24m fixed-clock|�n6�xin24m�2i2s@ff000000(rockchip,rk3328-i2srockchip,rk3066-i2s�� G�)7Ri2s_clki2s_hclk� �txrx �disabledi2s@ff010000(rockchip,rk3328-i2srockchip,rk3066-i2s�� G�*8Ri2s_clki2s_hclk�  �txrx �disabledi2s@ff020000(rockchip,rk3328-i2srockchip,rk3066-i2s�� G�+9Ri2s_clki2s_hclk� �txrx �disabledspdif@ff030000rockchip,rk3328-spdif�� G�.: Rmclkhclk� �tx�default�  �disabledpdm@ff040000 rockchip,pdm���=RRpdm_clkpdm_hclk� �rx�defaultsleep� � �disabledsyscon@ff100000&rockchip,rk3328-grfsysconsimple-mfd��+�1io-domains"rockchip,rk3328-io-voltage-domain �disabledpower-controller!rockchip,rk3328-power-controller�+power-domain@6�power-domain@5�power-domain@8�reboot-modesyscon-reboot-mode���RB� RB�RB� )RB�serial@ff110000&rockchip,rk3328-uartsnps,dw-apb-uart�� G7�&�Rbaudclkapb_pclk�  �txrx�default �5B �disabledserial@ff120000&rockchip,rk3328-uartsnps,dw-apb-uart�� G8�'�Rbaudclkapb_pclk�  �txrx�default �5B �disabledserial@ff130000&rockchip,rk3328-uartsnps,dw-apb-uart�� G9�(�Rbaudclkapb_pclk�  �txrx�default�5B�okayi2c@ff150000(rockchip,rk3328-i2crockchip,rk3399-i2c�� G$+�7� Ri2cpclk�default� �disabledi2c@ff160000(rockchip,rk3328-i2crockchip,rk3399-i2c�� G%+�8� Ri2cpclk�default��okaypmic@18rockchip,rk805� G|�xin32krk805-clkout2L\�default� h��!�!�!�!�"�"regulatorsDCDC_REG1 �vdd_logic� �4 2regulator-state-memD\B@DCDC_REG2�vdd_arm� �4 2�regulator-state-memD\~�DCDC_REG3�vcc_ddr2regulator-state-memDDCDC_REG4�vcc_io�2Z�2Z�2�"regulator-state-memD\2Z�LDO_REG1�vcc_18�w@w@2regulator-state-memD\w@LDO_REG2 �vcc18_emmc�w@w@2regulator-state-memD\w@LDO_REG3�vdd_10�B@B@2regulator-state-memD\B@i2c@ff170000(rockchip,rk3328-i2crockchip,rk3399-i2c�� G&+�9� Ri2cpclk�default�# �disabledi2c@ff180000(rockchip,rk3328-i2crockchip,rk3399-i2c�� G'+�:� Ri2cpclk�default�$ �disabledspi@ff190000(rockchip,rk3328-spirockchip,rk3066-spi�� G1+� �Rspiclkapb_pclk�  �txrx�default�%&'( �disabledwatchdog@ff1a0000 snps,dw-wdt�� G(pwm@ff1b0000rockchip,rk3328-pwm���<� Rpwmpclk�default�)x �disabledpwm@ff1b0010rockchip,rk3328-pwm���<� Rpwmpclk�default�*x �disabledpwm@ff1b0020rockchip,rk3328-pwm�� �<� Rpwmpclk�default�+x �disabledpwm@ff1b0030rockchip,rk3328-pwm��0 G2�<� Rpwmpclk�default�,x �disabledthermal-zonessoc-thermal������-tripstrip-point0�p���passivetrip-point1�L���passive�.soc-crit�s�� �criticalcooling-mapsmap0�. ����������tsadc@ff250000rockchip,rk3328-tsadc��% G:$�P�$�Rtsadcapb_pclk�initdefaultsleep�/�0&/0B 7tsadc-apbC1P��g�okay�-efuse@ff260000rockchip,rk3328-efuse��&P+�> Rpclk_efuse} id@7�cpu-leakage@17�logic-leakage@19�cpu-version@1a��adc@ff280000.rockchip,rk3328-saradcrockchip,rk3399-saradc��( GP��%�Rsaradcapb_pclk0V 7saradc-apb �disabledgpu@ff300000"rockchip,rk3328-maliarm,mali-450��0TGZW]XY[\"�gpgpmmupppp0ppmmu0pp1ppmmu1��� Rbuscore0fiommu@ff330200rockchip,iommu��3 G` �h265e_mmu��� Raclkiface� �disablediommu@ff340800rockchip,iommu��4@ Gb �vepu_mmu��F Raclkiface� �disablediommu@ff350800rockchip,iommu��5@ G �vpu_mmu��F Raclkiface� �disablediommu@ff360480rockchip,iommu ��6�@�6�@ GJ �rkvdec_mmu��B Raclkiface� �disablediommu@ff373f00rockchip,iommu��7? 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