� ��� 8�x( ��@ *,rockchip,rk3568-odroid-m1rockchip,rk35687Hardkernel ODROID-M1aliases=/pinctrl/gpio@fdd60000C/pinctrl/gpio@fe740000I/pinctrl/gpio@fe750000O/pinctrl/gpio@fe760000U/pinctrl/gpio@fe770000[/i2c@fe5c0000`/i2c@fe5a0000e/i2c@fe5b0000j/i2c@fdd40000o/i2c@fe5d0000t/i2c@fe5e0000y/serial@fe650000�/serial@fdd50000�/serial@fe660000�/serial@fe670000�/serial@fe680000�/serial@fe690000�/serial@fe6a0000�/serial@fe6b0000�/serial@fe6c0000�/serial@fe6d0000�/spi@fe610000�/spi@fe620000�/spi@fe630000�/spi@fe640000�/ethernet@fe2a0000�/mmc@fe310000�/mmc@fe2b0000cpus cpu@0�cpu,arm,cortex-a55�psci%9D cpu@100�cpu,arm,cortex-a55�psci%9D cpu@200�cpu,arm,cortex-a55�psci%9D cpu@300�cpu,arm,cortex-a55�psci%9D opp-table-0,operating-points-v2LDopp-408000000WQ� ^ �� ���0l�@opp-600000000W#�F ^ �� ���0opp-816000000W0�, ^ �� ���0}opp-1104000000WAʹ ^ �� ���0opp-1416000000WTfr ^ �� ���0opp-1608000000W_�" ^�����0opp-1800000000WkI� ^���0opp-1992000000Wv�� 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,arm,gic-v3 ��@�F  ��A(&Dusb@fd800000 ,generic-ehci��� ������usb�okayusb@fd840000 ,generic-ohci��� ������usb�okayusb@fd880000 ,generic-ehci��� ������usb�okayusb@fd8c0000 ,generic-ohci��� ������usb�okaysyscon@fdc20000),rockchip,rk3568-pmugrfsysconsimple-mfd���D�io-domains&,rockchip,rk3568-pmu-io-voltage-domain�okay5CQ_m{���syscon@fdc50000��� ,rockchip,rk3568-pipe-grfsysconD�syscon@fdc60000&,rockchip,rk3568-grfsysconsimple-mfd���Dsyscon@fdc80000$,rockchip,rk3568-pipe-phy-grfsyscon���D�syscon@fdc90000$,rockchip,rk3568-pipe-phy-grfsyscon���D�syscon@fdca0000#,rockchip,rk3568-usb2phy-grfsyscon����D�syscon@fdca8000#,rockchip,rk3568-usb2phy-grfsyscon��ʀ�D�clock-controller@fdd00000,rockchip,rk3568-pmucru�����Dclock-controller@fdd20000,rockchip,rk3568-cru���xin24m����G�� ���Di2c@fdd40000(,rockchip,rk3568-i2crockchip,rk3399-i2c��� .- i2cpclk`jdefault �okayregulator@1c ,tcs,tcs4525��vdd_cpu2D 5\�0t�� Dregulator-state-mem�pmic@20,rockchip,rk809� !�H���mclkHjdefault`"#���    & 2 > J V bD�regulatorsDCDC_REG1 vdd_logic2p ���D� \�ptqregulator-state-mem�DCDC_REG2vdd_gpup ���D� \�ptqDEregulator-state-mem�DCDC_REG3vcc_ddr2�regulator-state-mem�DCDC_REG4vdd_npup ���D� \�ptqregulator-state-mem�DCDC_REG5vcc_1v82Dw@\w@Dregulator-state-mem�LDO_REG1vdda0v9_imageD ��\ ��DRregulator-state-mem�LDO_REG2 vdda_0v92D ��\ ��regulator-state-mem�LDO_REG3 vdda0v9_pmu2D ��\ ��regulator-state-mem�� ��LDO_REG4 vccio_acodec2D2Z�\2Z�Dregulator-state-mem�LDO_REG5 vccio_sdDw@\2Z�Dregulator-state-mem�LDO_REG6 vcc3v3_pmu2D2Z�\2Z�Dregulator-state-mem��2Z�LDO_REG7 vcca_1v82Dw@\w@D�regulator-state-mem�LDO_REG8 vcca1v8_pmu2Dw@\w@regulator-state-mem��w@LDO_REG9vcca1v8_imageDw@\w@DSregulator-state-mem�SWITCH_REG1vcc_3v32Dregulator-state-mem�SWITCH_REG2 vcc3v3_sdD[regulator-state-mem�serial@fdd50000&,rockchip,rk3568-uartsnps,dw-apb-uart��� t ,baudclkapb_pclk�$$`%jdefault�� �disabledpwm@fdd70000(,rockchip,rk3568-pwmrockchip,rk3328-pwm��� 0 pwmpclk`&jdefault� �disabledpwm@fdd70010(,rockchip,rk3568-pwmrockchip,rk3328-pwm��� 0 pwmpclk`'jdefault� �disabledpwm@fdd70020(,rockchip,rk3568-pwmrockchip,rk3328-pwm���  0 pwmpclk`(jdefault� �disabledpwm@fdd70030(,rockchip,rk3568-pwmrockchip,rk3328-pwm���0 0 pwmpclk`)jdefault� �disabledpower-management@fdd90000&,rockchip,rk3568-pmusysconsimple-mfd���power-controller!,rockchip,rk3568-power-controller� Dpower-domain@7�*�power-domain@8��� +,-�power-domain@9� ��� ./0�power-domain@10� ��123456�power-domain@11� �7�power-domain@13� 8�power-domain@14� 9:;�power-domain@15� <=>?@ABC�gpu@fde60000&,rockchip,rk3568-maliarm,mali-bifrost���@$()' jobmmugpugpubus%D��okay&ED�video-codec@fdea0400,rockchip,rk3568-vpu��� ��� aclkhclk2F� iommu@fdea0800,rockchip,rk3568-iommu���@ � aclkiface��� 9DFvideo-codec@fdee0000,rockchip,rk3568-vepu��� @�� aclkhclk2G� iommu@fdee0800,rockchip,rk3568-iommu���@ ?�� aclkiface� 9DGmmc@fe0000000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc��@ d ����biuciuciu-driveciu-sampleFQ�р��_reset �disabledethernet@fe010000&,rockchip,rk3568-gmacsnps,dwmac-4.20a�� macirqeth_wake_irq@��������Wstmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_ref�� _stmmaceth�kH{�I�J� �disabledmdio,snps,dwmac-mdio stmmac-axi-config���DHrx-queues-config�DIqueue0tx-queues-config�DJqueue0vop@fe040000 ��0�@vopgamma-lut �(�����%aclkhclkdclk_vp0dclk_vp1dclk_vp22K� ��okay,rockchip,rk3568-vop����ports Dport@0� endpoint@2�LDTport@1� port@2� iommu@fe043e00,rockchip,rk3568-iommu ��>�? ��� aclkiface9�okayDKdsi@fe060000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsi�� D pclkhclk���dphy�M� _apb�� �disabledports port@0�port@1�dsi@fe070000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsi�� E pclkhclk���dphy�N� _apb�� �disabledports port@0�port@1�hdmi@fe0a0000,rockchip,rk3568-dw-hdmi��  -(���(�iahbisfrcecrefjdefault `OPQ� ����okay+R;SDports port@0�endpointTDLport@1�endpointUD�qos@fe128000,rockchip,rk3568-qossyscon��� D*qos@fe138080,rockchip,rk3568-qossyscon���� D9qos@fe138100,rockchip,rk3568-qossyscon��� D:qos@fe138180,rockchip,rk3568-qossyscon���� D;qos@fe148000,rockchip,rk3568-qossyscon��� D+qos@fe148080,rockchip,rk3568-qossyscon���� D,qos@fe148100,rockchip,rk3568-qossyscon��� D-qos@fe150000,rockchip,rk3568-qossyscon�� D7qos@fe158000,rockchip,rk3568-qossyscon��� D1qos@fe158100,rockchip,rk3568-qossyscon��� D2qos@fe158180,rockchip,rk3568-qossyscon���� D3qos@fe158200,rockchip,rk3568-qossyscon��� D4qos@fe158280,rockchip,rk3568-qossyscon���� D5qos@fe158300,rockchip,rk3568-qossyscon��� D6qos@fe180000,rockchip,rk3568-qossyscon�� qos@fe190000,rockchip,rk3568-qossyscon�� D<qos@fe190280,rockchip,rk3568-qossyscon��� D@qos@fe190300,rockchip,rk3568-qossyscon�� DAqos@fe190380,rockchip,rk3568-qossyscon��� DBqos@fe190400,rockchip,rk3568-qossyscon�� DCqos@fe198000,rockchip,rk3568-qossyscon��� D8qos@fe1a8000,rockchip,rk3568-qossyscon��� D.qos@fe1a8080,rockchip,rk3568-qossyscon���� D/qos@fe1a8100,rockchip,rk3568-qossyscon��� D0pcie@fe260000,rockchip,rk3568-pcie0��@�&?dbiapbconfig<KJIHGsyspmcmsilegacyerrK(�����$aclk_mstaclk_slvaclk_dbipclkaux�pciU`hVVVVv������ �pcie-phy�8x>�>�>���_pipe  �disabledlegacy-interrupt-controller� HDVmmc@fe2b00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc��+@ b ����biuciuciu-driveciu-sampleFQ�р��_reset�okay�� �!�jdefault`WXYZ�[mmc@fe2c00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc��,@ c ����biuciuciu-driveciu-sampleFQ�р��_reset �disabledspi@fe300000 ,rockchip,sfc��0@ exvclk_sfchclk_sfc`\jdefault�okay flash@0,jedec,spi-nor���->partitions,fixed-partitions partition@0OSPL�partition@e0000 OU-Boot Env�partition@100000OU-Boot� partition@300000Osplash�0partition@400000 OFilesystem�@�mmc@fe310000,rockchip,rk3568-dwcmshc��1 �{}� ��n6(|zy{}corebusaxiblocktimer�okay�Q ��Ujdefault`]^_`ai2s@fe400000,rockchip,rk3568-i2s-tdm��@ 4�=A�F�qF�q?C9mclk_txmclk_rxhclk�bctx�PQ _tx-mrx-m���okayDi2s@fe410000,rockchip,rk3568-i2s-tdm��A 5�EI�F�qF�qGK:mclk_txmclk_rxhclk�bbcrxtx�RS _tx-mrx-m�jdefault0`cdefghijklmn��okaymD�i2s@fe420000,rockchip,rk3568-i2s-tdm��B 6�M�F�qOO;mclk_txmclk_rxhclk�bbctxrx�T_m�jdefault`opqr� �disabledi2s@fe430000,rockchip,rk3568-i2s-tdm��C 7SW<mclk_txmclk_rxhclk�bbctxrx�UV _tx-mrx-m�� �disabledpdm@fe440000,rockchip,rk3568-pdm��D LZYpdm_clkpdm_hclk�b crx`stuvwxjdefault�X_pdm-m� �disabledspdif@fe460000,rockchip,rk3568-spdif��F f mclkhclk_\�bctxjdefault`y� �disableddma-controller@fe530000,arm,pl330arm,primecell��S@ �  apb_pclk�D$dma-controller@fe550000,arm,pl330arm,primecell��U@�  apb_pclk�Dbi2c@fe5a0000(,rockchip,rk3568-i2crockchip,rk3399-i2c��Z /HG i2cpclk`zjdefault  �disabledi2c@fe5b0000(,rockchip,rk3568-i2crockchip,rk3399-i2c��[ 0JI i2cpclk`{jdefault  �disabledi2c@fe5c0000(,rockchip,rk3568-i2crockchip,rk3399-i2c��\ 1LK i2cpclk`|jdefault  �disabledi2c@fe5d0000(,rockchip,rk3568-i2crockchip,rk3399-i2c��] 2NM i2cpclk`}jdefault  �disabledi2c@fe5e0000(,rockchip,rk3568-i2crockchip,rk3399-i2c��^ 3PO i2cpclk`~jdefault  �disabledwatchdog@fe600000 ,rockchip,rk3568-wdtsnps,dw-wdt��` � tclkpclkspi@fe610000(,rockchip,rk3568-spirockchip,rk3066-spi��a gRQspiclkapb_pclk�$$ctxrxjdefault `��  �disabledspi@fe620000(,rockchip,rk3568-spirockchip,rk3066-spi��b hTSspiclkapb_pclk�$$ctxrxjdefault `���  �disabledspi@fe630000(,rockchip,rk3568-spirockchip,rk3066-spi��c iVUspiclkapb_pclk�$$ctxrxjdefault `���  �disabledspi@fe640000(,rockchip,rk3568-spirockchip,rk3066-spi��d jXWspiclkapb_pclk�$$ctxrxjdefault `���  �disabledserial@fe650000&,rockchip,rk3568-uartsnps,dw-apb-uart��e ubaudclkapb_pclk�$$`�jdefault�� �disabledserial@fe660000&,rockchip,rk3568-uartsnps,dw-apb-uart��f v# baudclkapb_pclk�$$`�jdefault���okayserial@fe670000&,rockchip,rk3568-uartsnps,dw-apb-uart��g w'$baudclkapb_pclk�$$`�jdefault�� �disabledserial@fe680000&,rockchip,rk3568-uartsnps,dw-apb-uart��h x+(baudclkapb_pclk�$$ `�jdefault�� �disabledserial@fe690000&,rockchip,rk3568-uartsnps,dw-apb-uart��i y/,baudclkapb_pclk�$ $ `�jdefault�� �disabledserial@fe6a0000&,rockchip,rk3568-uartsnps,dw-apb-uart��j z30baudclkapb_pclk�$ $ `�jdefault�� �disabledserial@fe6b0000&,rockchip,rk3568-uartsnps,dw-apb-uart��k {74baudclkapb_pclk�$$`�jdefault�� �disabledserial@fe6c0000&,rockchip,rk3568-uartsnps,dw-apb-uart��l |;8baudclkapb_pclk�$$`�jdefault�� �disabledserial@fe6d0000&,rockchip,rk3568-uartsnps,dw-apb-uart��m }?<baudclkapb_pclk�$$`�jdefault�� �disabledthermal-zonescpu-thermal�d����tripscpu_alert0�p���passiveD�cpu_alert1�$����passivecpu_crit�s�� �criticalcooling-mapsmap0��0� �������� �������� �������� ��������gpu-thermal�����tripsgpu-threshold�p���passivegpu-target�$����passiveD�gpu-crit�s�� �criticalcooling-mapsmap0�� ����������tsadc@fe710000,rockchip,rk3568-tsadc��q s��f@ �`tsadcapb_pclk����� sjinitdefaultsleep`� � *� 4�okay J aD�saradc@fe720000.,rockchip,rk3568-saradcrockchip,rk3399-saradc��r ]saradcapb_pclk�� _saradc-apb |�okay ��pwm@fe6e0000(,rockchip,rk3568-pwmrockchip,rk3328-pwm��nZY pwmpclk`�jdefault� �disabledpwm@fe6e0010(,rockchip,rk3568-pwmrockchip,rk3328-pwm��nZY pwmpclk`�jdefault� �disabledpwm@fe6e0020(,rockchip,rk3568-pwmrockchip,rk3328-pwm��n ZY pwmpclk`�jdefault� �disabledpwm@fe6e0030(,rockchip,rk3568-pwmrockchip,rk3328-pwm��n0ZY pwmpclk`�jdefault� �disabledpwm@fe6f0000(,rockchip,rk3568-pwmrockchip,rk3328-pwm��o]\ pwmpclk`�jdefault� �disabledpwm@fe6f0010(,rockchip,rk3568-pwmrockchip,rk3328-pwm��o]\ pwmpclk`�jdefault� �disabledpwm@fe6f0020(,rockchip,rk3568-pwmrockchip,rk3328-pwm��o ]\ pwmpclk`�jdefault� �disabledpwm@fe6f0030(,rockchip,rk3568-pwmrockchip,rk3328-pwm��o0]\ pwmpclk`�jdefault� �disabledpwm@fe700000(,rockchip,rk3568-pwmrockchip,rk3328-pwm��p`_ pwmpclk`�jdefault� �disabledpwm@fe700010(,rockchip,rk3568-pwmrockchip,rk3328-pwm��p`_ pwmpclk`�jdefault� �disabledpwm@fe700020(,rockchip,rk3568-pwmrockchip,rk3328-pwm��p `_ pwmpclk`�jdefault� �disabledpwm@fe700030(,rockchip,rk3568-pwmrockchip,rk3328-pwm��p0`_ pwmpclk`�jdefault� �disabledphy@fe830000,rockchip,rk3568-naneng-combphy���"} refapbpipe�"����� �� �� ��okay ��Dphy@fe840000,rockchip,rk3568-naneng-combphy���%~ refapbpipe�%����� �� �� ��okayDphy@fe870000,rockchip,rk3568-csi-dphy���ypclk ���_apb� �disabledmipi-dphy@fe850000,rockchip,rk3568-dsi-dphy��� refpclkz �� _apb�� �disabledDMmipi-dphy@fe860000,rockchip,rk3568-dsi-dphy��� refpclk{ �� _apb�� �disabledDNusb2phy@fe8a0000,rockchip,rk3568-usb2phy���phyclkMclk_usbphy0_480m � ����okayhost-port ��okay ��Dotg-port ��okay ��Dusb2phy@fe8b0000,rockchip,rk3568-usb2phy���phyclkMclk_usbphy1_480m � ����okayhost-port ��okay ��Dotg-port ��okay ��Dpinctrl,rockchip,rk3568-pinctrl� �� xgpio@fdd60000,rockchip,gpio-bank��� !.  � �D!gpio@fe740000,rockchip,gpio-bank��t "cd � �gpio@fe750000,rockchip,gpio-bank��u #ef � �D�gpio@fe760000,rockchip,gpio-bank��v $gh � �D�gpio@fe770000,rockchip,gpio-bank��w %ij � �D�pcfg-pull-up D�pcfg-pull-none D�pcfg-pull-none-drv-level-1  +D�pcfg-pull-none-drv-level-2  +D�pcfg-pull-none-drv-level-3  +D�pcfg-pull-up-drv-level-1  +D�pcfg-pull-up-drv-level-2  +D�pcfg-pull-none-smt  :D�acodecaudiopwmbt656bt1120camcan0can1can2cifclk32kclk32k-out0 O�D cpuebcedpdpemmcemmc-rstnout O�Daemmc-bus8� O � �������D]emmc-clk O�D^emmc-cmd O�D_emmc-datastrobe O�D`eth0eth1flashfspifspi-dual-io-pins@ O����D\gmac0gmac0-miim O��D�gmac0-rx-bus20 O���D�gmac0-tx-bus20 O � � �D�gmac0-rgmii-clk O��D�gmac0-rgmii-bus@ O����D�gmac1gpuhdmitxhdmitxm0-cec O�DQhdmitx-scl O�DOhdmitx-sda O�DPi2c0i2c0-xfer O � �Di2c1i2c1-xfer O � �Dzi2c2i2c2m0-xfer O ��D{i2c3i2c3m0-xfer O��D|i2c4i2c4m0-xfer O � �D}i2c5i2c5m0-xfer O � �D~i2s1i2s1m0-lrckrx O�Dfi2s1m0-lrcktx O�Dei2s1m0-mclk O�D#i2s1m0-sclkrx O�Ddi2s1m0-sclktx O�Dci2s1m0-sdi0 O �Dgi2s1m0-sdi1 O �Dhi2s1m0-sdi2 O �Dii2s1m0-sdi3 O�Dji2s1m0-sdo0 O�Dki2s1m0-sdo1 O�Dli2s1m0-sdo2 O �Dmi2s1m0-sdo3 O �Dni2s2i2s2m0-lrcktx O�Dpi2s2m0-sclktx O�Doi2s2m0-sdi O�Dqi2s2m0-sdo O�Dri2s3ispjtaglcdcmcunpupcie20pcie30x1pcie30x2pdmpdmm0-clk O�Dspdmm0-clk1 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